Intel’s Core Ultra Series 3 for mobile platforms (aka “Panther Lake”) represents an evolution and not a revolution when compared to its predecessor, the Core Ultra Series 2 for mobile platforms (aka “Arrow Lake”). So while one should set their expectations appropriatel,y it is not necessarily a bad thing either. A measured and rational progression of improvement allows Intel to keep what worked, throw out what did not, and modify the “in-betweens” that have merit but missed their mark in the previous iterations of their grand vision for the future of computing.
To be precise, for the past few generations, Intel’s focus has been… efficiency-centric. However, Intel’s resulting bold move to combine a hybrid core strategy (aka P+E cores) with a disaggregated processor architecture did have teething issues—namely, notable thermal and scalability limitations. To put it in layman’s terms, Intel ran into the age-old problem of running out of room on the silicon (aka the “base tile”). This, in turn, meant that the number of Performance vs. Efficiency cores (and the total core count in the Compute Tile) was in direct competition with the iGPU core count, which was also competing with the NPU… which was also competing with the Platform Controller Tile (or what was once called the “SoC” Tile). All four were also competing for a bigger share of the TDP pie.
In what some will consider an interesting move, Panther Lake continues this four-tile MCM approach with its inherent… issues. Yes, that means they have not opted for a more “chiplet-style” approach to even the CPU/Compute tile design. As such, instead of using multiple “small” Compute tiles containing either “Little” (variants of E-cores) or “Big” (P-cores) clusters—as many thought they would do after the release of Lunar Lake—Intel has gone back to the Arrow Lake-era “Big Compute Tile” design.
With that said, Panther Lake is not just a “cut ‘n’ paste” of Arrow Lake with the underlying E-core and P-core architectures upgraded. No; instead, Intel has actually gone for a… hybrid approach. It’s one that tries to combine the best of Arrow Lake with that of Lunar Lake. Put another way, Intel is trying to blend the raw performance that Arrow Lake (the standard 2-series mobile processors) offered, but without the thermal penalty of said architecture—which often kept that performance in the realm of theory—by baking in the efficiency improvements of Lunar Lake (aka the ultra-low-power 2-series mobile CPUs released after the main 2-series launch).
To do this, a lot has changed. For example, in the P-core and E-core design, we see this new “efficiency and consistency trumps theoretical performance” philosophy in action. In fact, with Panther Lake, we actually see a reduction in the number of P-cores from six to four on the top-tier “16-core” mobile SKUs like the 388H! However, the underlying design of Cougar Cove has multiple notable improvements that (typically) make up for this reduction when compared to Lion Cove.
Yes, on just a cursory glance, this does not compute. A moderate IPC uplift (roughly 5–10%) does not make for a “faster” processor when said “new and shiny” model is running at lower frequencies and has fewer cores on tap compared to the older series. To be precise, the new Cougar Cove Performance cores are clocking in at “up to” 5.1GHz… compared to Lion Cove rocking an “up to” 5.4GHz boost rating. This, ironically, translates into a reduction of about 5.6 percent, which in theory nullifies nearly all the IPC gains… and still leaves Cougar Cove two P-cores short.
The devil, however, is in the details, and the reality is rather nuanced in this “tick” to the last-gen “tock” design. For example, the last-gen Lion Cove architecture introduced a split-tier L0/L1 cache that was optimized for the ultra-low power envelope of Lunar Lake. Now, in Cougar Cove, those Lunar Lake improvements have been further refined—and paired with the TDP headroom to really get the party started. Here alone, one will find further improved prefetching on the L1 Data cache and even better metadata on the L1 Instruction cache. To be precise, the Series 2 processors (both versions) used a modified version of traditional Stride and Stream prefetchers, which are great for recognizing linear patterns (e.g., “1…2…3…?”—if you said “4,” you get the idea) but are not great at guessing non-linear data. For example, 3D textures are not linear in nature, but they aren’t entirely random either; they are “blocks” that follow larger rulesets than simplistic linear code.
Thus, the 3-series’ Cougar Cove is using a more adaptive prefetching algorithm for its L0 and L1 data caches. It’s one that can, and does, perform typical pattern recognition in the current and previous data sets, but then ups the ante by also analyzing neighboring memory addresses to identify “bursty” workloads like AI/ML databases and handle these unique loads more efficiently with more consistent performance. This possibly results in as much as 20% more accurate prefetching, which in turn reduces the need to pull from the ~17-cycle L2 cache rather than the 3-cycle or 9-cycle caches.
On the instruction side, previous algorithms used fairly basic data tags for the L1 instruction cache. This is good in that you can use more room for data, but the downside is that it takes cycles for the 18-wide dispatch engine to decode and direct it properly. With the 3-series, each chunk gets a metadata tag that… partially pre-decodes that chunk of data to reduce latency by one or even two cycles during the fetch-to-decode stage. Mix in an algorithm that can use those metadata chunks to more accurately guess future demands, and the branch prediction engine becomes more accurate than ever before—further reducing the chances of a cache miss and the need to fall back to the L2 cache. This, in turn, means more consistent performance than what the 2-series offered.
