Intel’s Core Ultra Series 3 for mobile platforms (aka “Panther Lake”) represents an evolution and not a revolution when compared to its predecessor, the Core Ultra Series 2 for mobile platforms (aka “Arrow Lake”). So while one should set their expectations appropriately, this is not necessarily a bad thing either. A measured and rational progression of improvements allows Intel to keep what worked, throw out what did not, and modify the “in-betweens” that have merit… but for whatever reason missed their mark in helping Intel achieve its grand vision for the future of mobile computing.
To be precise, for the past few generations, Intel’s focus has been… efficiency-centric. However, Intel’s resulting bold move to combine a hybrid core strategy (aka P+E cores) with a disaggregated processor architecture did have teething issues. Namely, notable thermal and scalability limitations. To put it in layman’s terms, Intel ran into the age-old problem of running out of room on the silicon (aka ‘base tile’). Which in turn meant that the number of Performance vs E-Cores vs total number of cores in the Compute Tile was in direct competition with the iGPU core count, which was also competing with the NPU… which was also competing with the Platform Controller Tile (or what was once called the “SoC” Tile). All four of which were also competing for a bigger share of the TDP pie.
In what some will consider an interesting move, Panther Lake continues this 4-tile MCM approach with its inherent… issues. Yes. That means they have not opted for a more… “chiplet” approach to even the CPU/ Compute tile design. As such, instead of multiple “small” Compute tiles with just either.Little (variants of e-cores) and. Big (p-cores) as many thought they would do after the release of Lunar Lake, Intel has gone back to the Arrow Lake era of. Big Compute Tile design.
With that said, Panther Lake is not just a cut ‘n’ paste of Arrow Lake with the underlying e and p core architecture upgraded. No, instead Intel has actually gone for a… hybrid approach. One that tries to combine the best of Arrow with the portions of Lunar Lake that worked. Put another way, Intel is trying to blend the theoretical performance that Arrow Lake (standard 2-series mobile processors) technically offered, but without the thermal penalty of said architecture by baking in the efficiency improvements of Lunar Lake (aka the ultra-low-power 2-series mobile CPUs released after the main 2-series was launched).
To do this, a lot has changed. For example, in the P and E cores design, we do see this new “efficiency and consistency trumps theoretical performance” philosophy in action. In fact, with Panther Lake, we see a reduction in the number of P-cores from 6 to 4 on the top-tier “16-core” mobile SKUs like the 388H. However, the underlying design of Cougar Cove has multiple notable improvements that (typically can) make up for this reduction when compared to Lion Cove.
Yes. On just a cursory glance, this does not compute. A moderate IPC uplift (roughly 5-10%) does not make for a “faster” processor when said new and shiny is running at lower frequencies and has fewer of them on tap compared to the older series. To be precise, the new Cougar Cove Performance cores are clocking in at ‘up to’ 5.1GHz (388H, 4.8GHz in the 358H)… compared to Lion Cove rocking a ‘up to’ 5.4GHz boost rating (albeit only 4.7GHz in the last gen 7-class). Which, ironically, translates into a reduction of about 5.6 percent (for the 388H). Which in theory nullifies nearly all the IPC gains… and still leaves Cougar Cove two p-cores short.
Thankfully… the Core Ultra X7-class options paint a much rosier picture… as the “358H” is literally just a Core Ultra X9 388H that has been downclocked (aka failed X9 binning) and given an even less high asking price. This matters because the last-gen Core Ultra 7 268V came with the same number of cores, clocked slightly lower, so all the extra goodness Intel baked into the Panther Lake X9-class option makes it an across-the-board win for the Panther Lake X7… which in turn makes the 358H an incredible value.
So what has Intel baked into their Core Ultra 300 series that makes this a rather nuanced ‘tick’ to the last gen ‘tock’ design? For example, last-gen Lion Cove gave us a split-tier L0/L1 cache that was then optimized for the ultra-low power envelope in Lunar Lake. Now in Cougar Cove, those improvements of Lunar Lake have been further refined… and with a TDP headroom to really get the party started. Here alone one will find (further) improved prefetching on the L1 Data cache, and even better metadata on the L1 instruction cache. To be precise, the series 2 (both versions) used a modified traditional Stride and Stream Prefetcher, which is great for recognizing linear patterns (e.g. “1…2…3…?” if you said 4, you get the idea) but not great at guessing non-linear data. For example, 3D textures are not linear in nature but not entirely random either, as they are ‘blocks’ that follow larger rulesets than simplistic linear code.
Thus 3-series’ Cougar Cove is using a more adaptive prefetching algorithm for its L0 and L1 data cache. One that can, and does, perform typical pattern recognition in the current and previous data sets, but then ups the ante by also analyzing the neighboring memory address to identify “bursty” workloads like AI/ML databases and handle these unique loads more efficiently with more consistent performance. Possibly resulting as a much as 20% more accurate pre-fetching. Which in turn reduces the need to go from pulling from the 3 cycle or 9 cycle caches to the ~17 cycle L2 cache.
On the instruction side, previous algos used fairly basic data tags for their L1 instruction cache. Which is good in that you can use more of the room for data, but the downside is it takes cycles for the 18-wide dispatch engine to decode it and direct it properly. With the 3-series, each chunk gets a metadata tag that… partially pre-decodes that chunk of data to reduce latency by 1 or even 2 cycles on the fetch to decode stage. Mix in an algorithm that can use those metadata chunks to more accurately guess future demands… and the branch prediction engine is even more accurate than ever before. Further reducing the chances of a missed hit and the need to fall back to the L2 cache. Which in turn means more consistent performance than the 2-series offered.
